1. Technical Field
The present invention relates generally to extracting attribute fail rates from convoluted systems and in particular, to a computer implemented method for extracting attribute fail rates from convoluted process and design systems using yield modeling and statistical analysis.
2. Description of Related Art
Yield modeling is a process for modeling manufactured semiconductor devices to determine a ratio of devices that pass electrical testing to the total number of devices being tested. This is usually expressed as a percentage of good parts from the whole tested (e.g. 97%). Semiconductor manufacturers will attempt to maximize test yields in order to reduce the number of units rejected, thereby increasing revenue and profitability. Given that electrical testing is at or near the end of a long and expensive manufacturing process, any small improvement in yield can have a large impact on the bottom line.
There are many types of yield models including the Poisson model, the Murphy model, and the Exponential model. The model chosen is usually based on actual test data experienced by the manufacturer. That is, actual data may be gathered and compared to various models to determine the best fit for improved yield predictions.
The Poisson yield model assumes a uniform distribution of randomly occurring defects. That is, if a wafer has N chips and a large number n of randomly occurring defects for a yield of n/N=m, then the probability P that a given chip contains k defects may be approximated by the Poisson distribution as P=e−m(mk/k!). This results in yield Y being the probability that a chip has no defects or k=0, so Y=e−m. If D is the chip defect density, then D=mA where A is the area of each chip and AD is the average number of defects per chip. As a result, the Poisson yield model is Y=e(−AD). The Murphy yield model assumes a triangular distribution of defects resulting in a yield equation of Y=[(1−e(−AD))/(AD)]2. The Exponential yield model assumes higher defect densities clustered in some regions of a wafer resulting in a yield equation Y=esqrt(AD). Other yield models may utilize different assumptions of the behavior of defects, alternative defect distributions, and different formulas for modeling yield.
Failure analysis is a process of collecting and analyzing data to determine the cause of a failure. In semiconductor manufacturing, it is the process of determining how or why a semiconductor device has failed. Semiconductor manufacturing processes involve complex physical and chemical interactions. As semiconductor manufacturing becomes more complex, it is becoming more difficult to identify and determine the cause of a failure. A variety of failure analysis techniques may be utilized including non-destructive and destructive techniques. Non-destructive techniques include optical microscopy, curve tracing and x-ray radiography. Destructive techniques include decapsulation, sectioning and focused ion beam imaging. The results of such non-destructive and destructive techniques can then be analyzed to determine a cause of the failure.